Design Verification Engineer – SystemVerilog/UVM

About the role

We are seeking a Design Verification Engineer with at least two years of experience to join our front‑end verification team. You will work on cutting‑edge ASIC and IP projects for a leading global semiconductor company, creating robust verification environments and driving coverage closure.

Key responsibilities

• Develop SystemVerilog/UVM testbenches for complex digital IPs.
• Create and execute verification test plans, including directed and constrained‑random test cases.
• Run RTL simulations, manage regression suites, and debug functional issues.
• Analyze functional coverage metrics and drive coverage closure.
• Collaborate closely with RTL designers to resolve design and verification problems.
• Participate in verification reviews and milestone deliveries.

Required profile

• 2+ years of hands‑on ASIC/SoC design verification experience.
• Strong understanding of digital design and RTL concepts.
• Good analytical and problem‑solving abilities.

Required skills

• SystemVerilog
• UVM methodology
• RTL simulation and debugging
• Functional coverage and constrained‑random verification
• Synopsys simulation tools (nice to have)
• Basic scripting in Python, Perl or Shell (nice to have)